1. Field of the Invention
Embodiments of the present invention relate to a method of forming a chip carrier substrate to alleviate chip and lead cracking, and a chip carrier formed thereby.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate. The substrate may in general include a rigid base having a conductive layer etched on one or both sides. Electrical connections are formed between the die and the conductive layer(s), and the conductive layer(s) provide an electric lead structure for integration of the die into an electronic system. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
In view of the small form factor requirements, as well as the fact that flash memory cards need to be removable and not permanently attached to a printed circuit board, such cards are often built of a land grid array (LGA) package. In an LGA package, the semiconductor die are electrically connected to exposed contact fingers formed on a lower surface of the package. External electrical connection with other electronic components on a host printed circuit board (PCB) is accomplished by bringing the contact fingers into pressure contact with complementary electrical pads on the PCB. LGA packages are ideal for flash memory cards in that they have a smaller profile and lower inductance than pin grid array (PGA) and ball grid array (BGA) packages.
A cross-section of a conventional LGA package (without molding compound) is shown in FIG. 1. One or more die 20 are mounted on a substrate 22 via die attach 24. The die are shown separated by a dielectric spacer layer 26. In embodiments, the die 22 may be affixed to dielectric spacer layer 26 by an epoxy. Generally, the substrate 22 is formed of a rigid core 28, of for example polyimide laminate. Thin film copper layer(s) 30 may be formed on the core in a desired electrical lead pattern, including exposed surfaces for the contact fingers, using known photolithography and etching processes. The contact fingers 32 may be formed of a layer of gold deposited on the copper layer 30 to provide the electrical connection of the package to the host PCB. The substrate may be coated with a solder mask 36, leaving the contact fingers 32 exposed, to insulate and protect the electrical lead pattern formed on the substrate. The solder mask covers the surfaces of the substrate, leaving exposed those areas that are to be soldered. The die may be electrically connected to the substrate by wire bonds 34. Vias 42 (FIG. 2) are formed through the substrate to allow electrical connection of the die through the substrate to the contact fingers 32. Further examples of typical LGA packages are disclosed in U.S. Pat. Nos. 4,684,184, 5,199,889 and 5,232,372, which patents are incorporated by reference herein in their entirety.
A bottom view of the substrate shown in prior art FIG. 1 is shown in prior art FIG. 2. As shown, the contact fingers 32 are generally rectangular with leads 40 extending from respective fingers to vias 42 or other electrical terminals. The contact fingers 32 also have plating traces 46 connecting each of the fingers 32 to a plating bar (not shown). The plating bar connects all of the contact fingers to the same electrical potential for plating during an electroplating process. In one such process, the substrate 22 is immersed in a plating bath including metal ions in an aqueous solution. A current is supplied to the plating bar, which current travels through the plating traces 46 to contact fingers 32. When the current is delivered, metal ions are attracted to the electrified and charged surfaces of the contact fingers. In this way, a layer of gold or other plating metal of a desired thickness may be deposited. After electroplating, the plating bar is removed leaving a portion of the plating traces 46 on the substrate 22.
After the die are mounted onto the substrate, the assembly is packaged within a molding compound to protect the assembly. During the molding process, the molding machine may output an injection force typically about 0.8 tons to drive the molding compound into the mold cavity. For die having a footprint of about 4.5 mm by 2.5 mm, this injection force may result in a pressure down on the die of about 1.2 kgf/mm2.
A portion of the die 20 overlie an edge of the contact fingers. The edges of all contact fingers define a straight line 54 beneath the die, where the height of the substrate is greater (owing to the contact fingers) on one side of line 54 than on the other side. Upon exertion of the molding force, the difference in height along straight line 54 defined by the contact finger edges generates mechanical stress on the semiconductor die.
In the past, semiconductor die were better able to withstand the stress generated during the molding process in LGA packages. However, chip scale packages (CSP) and the constant drive toward smaller form factor packages require very thin die. It is presently known to employ wafer backgrind during the semiconductor fabrication process to thin die to a range of about 2 mils to 13 mils. At these thicknesses, the die are often not able to withstand the stresses generated during the molding process. Therefore, the die can crack, for example along the line 54.
Die cracking under the stress of the molding process will generally result in the package having to be discarded. Occurring at the end of the semiconductor fabrication and packaging process, this is an especially costly and burdensome problem.
In addition to die cracking, the leads 40 connect to the contact fingers 32 at right angles. The abrupt change in the conductance pattern at the junction where a lead 40 connects to a contact finger 32 generates mechanical stress at that junction.
Moreover, as shown in prior art FIG. 3, the solder mask 36 is applied over the conductance pattern with openings for the contact fingers 32. The openings in the solder mask 36 at the contact fingers 32 begin at the junctions between the leads 40 (beneath the solder mask) and the contact fingers 32. Thus, the thickness of the substrate over the leads 40 (including the solder mask) is greater than the thickness of the substrate over the fingers 32 (not having the solder mask). This difference in thickness further generates mechanical stress at the junction between the leads 40 and the contact fingers 32.
Thus, mechanical stress is generated at the junction between the leads 40 and the contact fingers 32 both from the abrupt change in the patterns at the junction and the differences in substrate thicknesses at the junction. Over time, this mechanical stress can cause one or more of the leads 40 to break at or near the junction between the contact fingers and leads, resulting in package failure.
Separate and independent from the problem of die cracking and lead breaking, the portions of plating traces 46 remaining after the plating trace is severed from the contact fingers 32 tend to curl up over time. In particular, when a device formed from substrate 22 is used with a host device, the substrate contact fingers 32 are brought into pressure contact with pins on the host device. These host device pins often rub against the ends of plating traces 46. This contact may cause the ends of plating traces 46 to detach and curl up with repeated use of the flash memory device in a host device. While not a problem in and of itself, this curling of the plating traces 46 can cause one or more of the metal layers on the contact fingers 32 to delaminate from the substrate. This delamination of the contact finger layers may result in damage to the package and/or package failure.